Field of the Disclosure
The present disclosure relates to a display device, and more particularly, to a display device including power link lines formed between the output pads of a driving integrated circuit.
Discussion of the Related Art
An organic light-emitting diode (OLED) which is one of flat panel displays (FPDs), has the characteristics of high brightness and a low operating voltage.
The OLED has a high contrast ratio since it is a self-luminous device, can be implemented as an ultra thin display, can easily reproduce moving pictures due to its response time of several microseconds (μs), has no limitation of a viewing angle, and can stably operate at a low temperature. Also, since the OLED can be driven at a low direct current voltage of 5V to 15V, it is easy to manufacture and design a driving circuit with the OLED.
Furthermore, the OLED can be manufactured through a simple manufacturing process including only deposition and encapsulation.
However, since the OLED is a current mode of emitting light by supplying current to light-emitting diodes, it is necessary to supply various high voltages to individual pixel areas through an integrated power line.
The integrated power line of the OLED will be described with reference to FIGS. 1 and 2, below.
FIG. 1 shows an example of a conventional OLED display device 10, and FIG. 2 is an enlarged view of an area A of FIG. 1.
As shown in FIG. 1, the conventional OLED display device 10 includes a light-emitting diode panel 15 that displays images, and a plurality of gate drivers (not shown) and a plurality of data drivers 20 connected to the light-emitting diode panel 15 to supply gate signals and data signals, respectively.
The light-emitting diode panel 15 includes a display area DA consisting of a plurality of pixel areas P, and a non-display area NDA surrounding the display area DA. The display area DA includes a plurality of first power lines 54 for supplying a first voltage to the pixel areas P, and the non-display area NDA includes first integrated power lines 50 connected to the first power lines 54 to transfer the first voltage from an external source to the first power lines 54.
Although not shown in the drawings, the display area DA includes a plurality of second power lines for supplying a second voltage to the pixel areas P, and the non-display area NDA includes second integrated lines 52 connected to the second power lines to transfer the second voltage from an external source to the second power lines.
Each data driver 20 may be formed in the form of a chip on film (COF) in which a driving integrated circuit (DIC) 22 is mounted on a film, like a tape carrier package (TCP).
First power supply lines 40 to which the first voltage from the external source is supplied, are formed at both ends of the data driver 20, and the first power supply lines 40 are connected to one of the first integrated power line 50.
Also, a secondary driver 30 such as a film on glass (FOG) may be connected to the light-emitting diode panel 15, and a second power supply line 42 is connected to the secondary driver 30 and to one of the second integrated power lines 52.
In more detail, as shown in FIG. 2, the driving integrated circuit 22 of the data driver 20 includes a plurality of digital-analog converters DAC1, DAC2, DAC3, and DAC4, a plurality of buffers BF1, BF2, BF3, and BF4, and a plurality of output pads OP1, OP2, OP3, and OP4. The digital-analog converters DAC1, DAC2, DAC3, and DAC4, the buffers BF1, BF2, BF3, and BF4, and the output pads OP1, OP2, OP3, and OP4 are connected 1:1:1 to each other, and the output pads OP1, OP2, OP3, and OP4 are connected to a plurality of data lines 60 of the light-emitting diode panel 15.
Also, a plurality of data signals created by the digital-analog converters DAC1, DAC2, DAC3, and DAC4 are supplied to the data lines 60 through the buffers BF1, BF2, BF3, and BF4, and the output pads OP1, OP2, OP3, and OP4.
Also, the first power supply lines 40 are formed at both ends of the data driver 20, a power input pad 40a and a power output pad 40b are formed at both ends of each first power supply line 40, and the power output pad 40b is connected to the first integrated power line 50 of the light-emitting diode pad 15.
Meanwhile, a plurality of first power lines 54 are formed between the pixel areas P1, P2, P3, and P4 of the light-emitting diode panel 15, and the first power lines 54 are connected to the first integrated power line 50 to receive the first voltage from the first integrated power line 50.
FIG. 3 shows another example of a conventional OLED display device.
As shown in FIG. 3, the conventional OLED display device according to the other example includes a light-emitting panel 115 that displays images, and a plurality of gate drivers (not shown) and a plurality of data drivers 120 connected to the light-emitting diode panel 115 to supply gate signals and data signals, respectively.
The light-emitting diode panel 115 includes a display area DA consisting of a plurality of pixel areas P, and a non-display area NDA surrounding the display area DA. The display area DA includes a plurality of first power lines 154 and a plurality of second power lines (not shown) for supplying first and second voltages to the pixel areas P, and the non-display area NDA includes first integrated power lines 150 connected to the first power lines 154 to transfer the first voltage from an external source to the first power lines 154, and second integrated power lines 152 connected to the second power lines to transfer the second voltage from an external source to the second power lines.
Each data driver 120 may be formed in the form of a COF in which a driving integrated circuit (DIC) 22 is mounted on a film, like a TCP.
First external power lines 140 to which the first voltage from the external source is supplied, and second external power lines 142 to which the second voltage from the external is supplied, are formed at both ends of the data driver 120, and the first and second external power lines 140 and 142 are connected to ones of the first and second integrated power lines 150 and 152, respectively.
In the conventional OLED display devices 10 and 110, the first and second voltages may be a supply voltage VDD and a ground voltage VSS, respectively. Since the first and second voltages may be supplied to all pixel areas P of the light-emitting diode panels 15 and 115 through ones of the first integrated power lines 50 and 150 and ones of the second integrated power lines 52 and 152, an excessive amount of current comes to flow through the first integrated power lines 50 and 150 and the second integrated power lines 52 and 152.
Accordingly, the first integrated power lines 50 and 150 and the second integrated power lines 52 and 152 may be electrically open or burned, or electrically shorted with other lines due to the breakdown of their upper and lower insulating layers. The failure of the first integrated power lines 50 and 150 and the second integrated power lines 52 and 152 is propagated to the first power lines 54 and 154 and the second power lines.
In particular, in the case of a large size display requiring a larger amount of driving current, such a failure becomes a serious problem.